A methodology for hardware verification using compositional model checking

A methodology for hardware verification using compositional model checking

A methodology for system-level hardware veriication based on compositional model checking is described. This methodology relies on a simple set of proof techniques, and a domain speciic strategy for applying them. The goal of this strategy is to reduce the veriication of a large system to nite state subgoals that are tractable in both size and number. These subgoals are then discharged by model...

Hardware failure modelling methodology for model checking

Microarchitecture Verification by Compositional Model Checking

Compositional model checking is used to verify a processor microarchitecture containing most of the features of a modern microprocessor, including branch prediction, speculative execution, out-of-order execution and a load-store buffer supporting re-ordering and load forwarding. We observe that the proof methodology scales well, in that the incremental proof cost of each feature is low. The pro...

Compositional Reasoning for Hardware/Software Co-verification

In this paper, we present and illustrate an approach to compositional reasoning for hardware/software co-verification of embedded systems. The major challenges in compositional reasoning for co-verification include: (1) the hardware/software semantic gaps, (2) lack of common property specification languages for hardware and software, and (3) lack of compositional reasoning rules that are applic...

A Methodology for Large-Scale Hardware Verification

We present a formal verification methodology for datapathdominated hardware. This provides a systematic but flexible framework within which to organize the activities undertaken in large-scale verification efforts and to structure the associated code and proof-script artifacts. The methodology deploys a combination of model checking and lightweight theorem proving in higher-order logic, tightly...